High frequency power amplifier module, and wireless communications system

ABSTRACT

A high frequency power amplifier module of a multistage amplifier construction comprising: an input terminal; an output terminal; a control terminal; and a mode switching terminal. The first amplification stage includes a dual gate FET, and a bias voltage according to a signal is applied to the first gate and the second gate of the dual gate FET from the control terminal and the mode switching terminal, and a radio signal from the input terminal is applied to the second gate such as the source of the dual gate FET. In dependence upon the signal from the mode switching terminal, the mode of the high frequency power amplifier module is for the GSM (i.e., for a non-linear amplifying action) and for the EDGE (for a linear amplifying action).

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a high frequency power amplifiermodule (or a high frequency power amplifier) including a plurality ofamplification lines for linear amplifications and for non-linearamplifications (or saturated amplifications), and a wirelesscommunication system packaging the high frequency power amplifiermodule. More particularly, the invention relates to a techniqueeffective when applied to a multi-mode communication type cellularmobile phone having a plurality of communication functions of differentcommunication modes.

[0002] In North America, in recent years, there has been employed theso-called “dual mode mobile phone” in which there are incorporated intoone mobile phone: the analog type AMPS (Advanced Mobile Phone Service)employed in the prior art and covering the entire North America; and thedigital system such as the TDMA (Time Division Multiple Access) or theCDMA (Code Division Multiple Access).

[0003] In Europe and so on, on the other hand, there has been employedthe GSM (Global system for Mobile Communication) system using the TDMAtechnique and the FDD (Frequency Division Duplex) technique. In the GSMsystem, on the other hand, there has been developed the EDGE (EnhancedData Rates for GSM Evolution) system as the communication system capableof enhancing the transmission rate.

[0004] The multi-mode communications by the dual mode mobile phone orthe like are described, for example, on pp. 115 to 126 of “NIKKEIELECTRONICS” (No. 681), issued by NIKKEI BP on Jan. 27, 1997.

[0005] Into the wireless communication system (or the mobile phone),there is incorporated an amplifier (or the high frequency poweramplifier module) packaging transistors in multiple stages. Thecommunication system is seriously influenced by the performance of thehigh frequency power amplifier module.

[0006] In Japanese Patent Laid-Open No. 154321/1992, there is discloseda high frequency power amplifier which can control the high frequencyoutput power over a wide range while retaining the satisfactory linearcharacteristics and the power efficiency stably. This high frequencypower amplifier has a multistage construction using a MOSFET (MetalOxide Semiconductor Field Effect Transistor) or a GaAs-FET in the finalstage circuit so that the high frequency output power is variablycontrolled by changing the bias condition of the drive circuit from theoutside while keeping the bias of the final stage circuit constant.There is also disclosed a technique for controlling the output power byincorporating a variable attenuator circuit into a high frequency inputline of the aforementioned circuit.

[0007] In Japanese Patent Laid-Open No. 26776/1999, on the other hand,there is disclosed a power amplifier which can reduce the powerconsumption without increasing the distortion and can improve the powerefficiency. This power amplifier has a high frequency circuit employinga dual gate FET. This power amplifier is constructed such that twostages of dual gate FETs are cascade-connected between an input terminalIn and an output terminal OUT. Specifically, the first gate on the drainside of the dual gate FET at the first stage is connected with the inputterminal IN, and the drain is connected with the first gate on the drainside of the dual gate FET at the final stage. The drain of the dual gateFET at the final stage is connected with the output terminal OUT. Thefirst gates of the first stage and the final stage are connected with afirst gate input terminal G1, and the second gates of the first stageand the final stage are connected with a second gate input terminal G2.

SUMMARY OF THE INVENTION

[0008] Most wireless data communications, as used in the mobilecommunications, are effected at a transmission rate of 9.6 Kbps. Since ahigher transmission speed has been demanded for accessing to theinternets or data bases of enterprises, however, there has been needed acommunication system for the high speed. The GSM system servicing mainlyin Europe and Asia has the transmission rate of 9.6 Kbps at present. Inorder to satisfy the demands thus far described, however, there has beendeveloped the EDGE system having the high transmission rate. Byintroducing this system, the data transmission rate is raised to as highas 48 Kbps so that data of four times as high as that of the GSM systemcan be transmitted for a unit of time.

[0009] Another advantage of the EDGE system is that it can be runwithout introducing any new infrastructure because it is practiced byusing the basic system of the GSM with a partial change in the wirelessmodulation method. This little change is attractive for manycommunication businessmen.

[0010] For the modulation method, the GSM system adopts the GMSK(Gaussian Minimum Shift Keying) modulation, but the EDGE system adoptsthe 3π/8-rotating 8PSK (Phase Shift Keying) modulation. This means thechange from the GMSK modulation method to the 3π/8-rotating 8PSKmodulation method. For this change in the modulation method, the signaltransmission unit of the wireless communication system is required tohave a higher linearity.

[0011] Since the EDGE system is developed from the GSM system, onemobile phone can desirably communicate with the GSM system and the EDGEsystem. This makes it necessary to incorporate both an amplifier for theGSM system and an amplifier for the EDGE system in the mobile phone.

[0012] We have examined a high frequency power amplifier module whichcan cover both the GSM system and the EDGE system with one amplifier andhave found out the following problems to be solved.

[0013] (1) The transistor acts, when employed in the GSM, in thesaturated state so that a high power is demanded. For an input signal atabout 0 dBm, as modulated in the GMSK, an output power required is about36 dBm at the maximum.

[0014] (2) The transistor acts, when employed in the EDGE, in the linearstate so that a linearity is demanded. For an input signal modulated atthe 3π/8-rotating 8PSK, specifically, no distortion is required for theoutput signal. On the other hand, the maximum of the linear output poweris within a range of about 28 to 29 dBm.

[0015] (3) Since the GSM system and the EDGE system have a largedifference in the output power, as described above, it is questionablehow to realize the two system with the single amplifier. Specifically,the system for making the non-linear action and the linear actioncompatible is exemplified by the AMPS (for the saturated action)/theCDMA (for the linear action) of North America. In this case, the maximumoutput power is about 30 to 32 dBm for the AMPS but about 28 to 29 dBmfor the CDMA, so that the different is 2 to 3 dBm. Therefore, thecompatible system is easily enabled to match the two actions by makingthe input power variable, even if it is operated at the same biasvoltage. In the GSM/EDGE, however, the maximum power has a difference aslarge as 6 to 8 dBm so that the two system cannot be made compatiblewith one circuit.

[0016] (4) The mobile phone is powered by the battery so that it isrequired to a higher efficiency for a longer use. For example, the GSMis required to have an efficiency of about 50 to 60%, and the EDGE isrequired to have an efficiency of about 35 to 40%. This makes itdesirable to make the used power amplification element as small aspossible.

[0017] An object of the invention is to provide a high frequency poweramplifier module and a wireless communication system for making the GSMsystem (for the saturated action) and the EDGE system (for the linearaction) compatible in one circuit.

[0018] Another object of the invention is provide a high frequency poweramplifier module and a wireless communication system, which can improvethe AM modulation (or the AM-AM conversion).

[0019] Still another object of the invention is to provide a highfrequency power amplifier module and a wireless communication system,which can easily isolate input and output terminals while causing littlesignal leakage.

[0020] The foregoing and other objects and novel features of theinvention will become apparent from the description to be made withreference to the accompanying drawings.

[0021] The representative of the invention to be disclosed herein willbe briefly summarized in the following.

[0022] (1) According to an aspect of the invention, there is provided ahigh frequency power amplifier module having a multistage amplifierconstruction, in which a plurality of semiconductor amplificationelements are sequentially cascade-connected. The high frequency poweramplifier module includes at least an input terminal, an outputterminal, a control terminal and a mode switching terminal as itsexternal terminals. The amplification element at the first stage isexemplified by a dual gate FET, which is fed at a first gate G₁ close toits drain with a signal from the control terminal and at a second gateG₂ with a radio signal from the input terminal. To the second gate G₂,on the other hand, there is applied a bias voltage which is based on thesignal from the control terminal and a signal from the mode switchingterminal. In accordance with the signal from the mode switchingterminal, the high frequency power amplifier module is caused to act asan amplifying line for the GSM or an amplifying line for the EDGE. Inthis case, the amplifying line for the GSM system acts non-linearly sothat its output power is about 36 dBm at the maximum, and the amplifyingline for the EDGE system acts linearly so that its output power is about29 dBm at the maximum.

[0023] According to this means:

[0024] (a) the GSM system (for the saturated action) and the EDGE system(for the linear action) can be realized in the common circuit; and

[0025] (b) in the high frequency power amplifier module of themultistage amplifier construction, the input stage (or the first stage)is constructed to include a dual gate FET which is fed at its first gatewith a control voltage. As seen from a graph of FIG. 3, therefore, theAM-AM conversion (AMout) can be improved to 16% or less for an inputpower Pin of 6 dBm or higher.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026]FIG. 1 is a circuit diagram of a high frequency power amplifiermodule according to one embodiment (or Embodiment 1) of the invention;

[0027]FIG. 2 is a graph illustrating correlations between an externalcontrol voltage and a gate voltage in the high frequency power amplifiermodule packaging a dual gate FET according to Embodiment 1;

[0028]FIG. 3 is a graph plotting an AM modulation by the high frequencypower amplifier module of Embodiment 1;

[0029]FIG. 4 is a sectional view showing a sectional structure of aportion of the dual gate FET packaged in the high frequency poweramplifier module of Embodiment 1;

[0030]FIG. 5 is a circuit diagram schematically showing the highfrequency power amplifier module of one embodiment of the invention;

[0031]FIG. 6 is a block diagram schematically showing a construction ofa wireless communication system packaging the high frequency poweramplifier module of the embodiment;

[0032]FIG. 7 is a graph plotting isolation characteristics betweeninput/output terminals in the high frequency power amplifier moduleaccording to another embodiment (or Embodiment 2) of the invention;

[0033]FIG. 8 is a circuit diagram of a high frequency power amplifiermodule according to another embodiment (or Embodiment 3) of theinvention;

[0034]FIG. 9 is a graph illustrating correlations between an externalcontrol voltage and a gate voltage in a high frequency power amplifiermodule packaging a dual gate FET of Embodiment 3;

[0035]FIG. 10 is a circuit diagram of a high frequency power amplifiermodule according to another embodiment (or Embodiment 4) of theinvention;

[0036]FIG. 11 is a graph illustrating correlations between an externalcontrol voltage and a gate voltage in a high frequency power amplifiermodule packaging a dual gate FET of Embodiment 4.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] The invention will be described in detail in connection with itsembodiments with reference to the accompanying drawings. Throughout allthe drawings for explaining the embodiments of the invention, thecomponents having identical functions will be designated by the commonreference numerals, and their repeated description will be omitted.

[0038] (Embodiment 1)

[0039]FIG. 1 is a circuit diagram of a high frequency power amplifiermodule (or a high frequency power amplifier) according to one embodiment(or Embodiment 1) of the invention. Embodiment 1 will be described onthe case in which a semiconductor amplification element (or transistor)is exemplified by a dual gate field effect transistor (or dual gateFET).

[0040] A high frequency power amplifier module 1 of Embodiment 1 isprovided as its external electric terminals with: an input terminal 2 tobe fed with an input signal Pin (i.e., a signal to be amplified); anoutput terminal 3 for outputting an output signal Pout; a first voltageterminal 4 fixed at a first reference potential Vdd; a not-shown secondvoltage terminal fixed at a second reference potential Vss (e.g., at theground); and a control terminal 6 to which a variable voltage Vapc isapplied.

[0041] The high frequency power amplifier module 1 has a single stageamplifier construction for amplifications with one semiconductoramplification element (or transistor) or a multistage amplifierconstruction for individual amplifications with a plurality oftransistors which are sequentially cascade-connected. Embodiment 1 willbe described on the high frequency power amplifier module of the singlestage construction in which the dual gate FET is packaged as thetransistor.

[0042] A transistor T1, i.e., a dual gate FET 7 is connected at itssecond gate G₂ with the input terminal 2 through a microstrip line MS1.A capacitor C1 is connected in series between the microstrip line MS1and the input terminal 2, and a capacitor C3 is connected in parallelbetween the microstrip line MS1 and the ground (i.e., the secondreference potential. Vss).

[0043] Between a node b between a resistor R1 and the control terminal 6and a first gate G₁ of the dual gate FET 7, on the other hand, there isconnected in series a resistor R5 for setting the potential to beapplied to the first gate G₁.

[0044] With the second gate G₂ of the dual gate FET 7, on the otherhand, there are connected two resistors R1 and R2, of which the lowerpotential resistor R2 is connected with the ground whereas the higherpotential resistor R1 is connected with the control terminal 6, therebyto construct a resistance-type potential dividing circuit (or a breedercircuit). Between a node a between the two resistors R1 and R2 and thesecond gate G₂, on the other hand, there is connected a resistor R3 forsetting a potential to be applied to the second gate G₂. This resistorR3 is effective for suppressing such an impedance on the side of theresistance-type potential dividing circuit as will influence the secondgate G₂.

[0045] On the other hand, a drain terminal D or the first terminal ofthe dual gate FET 7 is connected with the first voltage terminal 4through microstrip lines MS3 and MS2 and with the output terminal 3through a microstrip line MS4 and a capacitor C2. To the first voltageterminal 4, there is applied the first reference potential Vdd as thepower voltage. On the other hand, the second terminal of the dual gateFET 7 acts as a source terminal S and is connected with the groundpotential (or the second reference potential Vss). Moreover, a capacitorC4 is connected between the microstrip line MS4 and the ground, althoughnot especially limitative thereto.

[0046] Here will be briefly described the construction of the dual gateFET 7 with reference to FIG. 4.

[0047] The dual gate FET 7 is made of either a compound semiconductorsuch as GaAs or Si (silicon) and will be described in Embodiment 1 onthe case in which it is exemplified by a Si-MOSFET. FIG. 4 is asectional view showing a cell portion of the dual gate FET 7, which isfabricated by doping a P-type epitaxial layer 21, as formed over on face(or upper face) of a substrate 20 of Si, selectively with predeterminedimpurity atoms to form an N-type (e.g., N⁺-type or N⁻-type) or P-type(e.g., P⁺-type) semiconductor region.

[0048] Specifically, a P-type well 22 is selectively formed in thesurface layer portion of the epitaxial layer 21, and N⁻-type regions 23are formed individually in the P-type well 22 and in the region from theP-type well 22 and outside of the P-type well 22. In FIG. 4, threeN⁻-type regions 23 a, 23 b and 23 c are arranged from left to right. TheN⁻-type region 23 c at the righthand end extends at its lefthand endportion into the P-type well 22. In the surface layer portions of theN⁻-type regions 23 a, 23 b and 23 c, there are formed N⁺-type regions 24(as indicated by 24 a, 24 b and 24 c from left to right) in the regionor at or slightly over one end of the region.

[0049] The surface layer portions of the P-type region between theN⁺-type region 24 a and the and N⁻-region 23 b and between the regionN⁺-type region 24 b and the N⁻-type region 23 c provide channels, overwhich there is individually formed gate insulating film 25 which isoverlaid by a first gate electrode 26 or a second gate electrode 27.

[0050] At the lefthand end portion, on the other hand, there are formeda P⁺-type region 28 depthwise extending through the epitaxial layer 21to the surface layer portion of the substrate 20, and a P⁺-type region29 depthwise extending to the surface layer portion of the P-type well22. Of these, the P+type region 28 is formed on the lefthand side frommidway of the N⁺-type region 24 a at the lefthand end portion, and theP⁺-type region 29 is so formed on the lefthand side from the lefthandend portion of the N⁺-type region 24 a as to overlie the N⁻-type region23.

[0051] On the other hand, the epitaxial layer 21 (or the substrate 20)is covered on its surface with an insulating film forming the gateinsulating film 25 and a layer insulating film 30 formed over the formerinsulating film. This layer insulating film 30 covers the first gateelectrode 26 and the second gate electrode 27, too.

[0052] In the layer insulating film 30 over the N⁺-type regions 24 a and24 c and the P⁺-type region 29, there are formed contact holes, and theelectrodes are selectively disposed over the contact holes and the layerinsulating film 30. Of these, the electrode over the N⁺-type region 24 cprovides a drain electrode 31, and both the electrodes over the N⁺-typeregion 24 a and the P⁺-type region 29 are connected over the layerinsulating film 30 to provide a source electrode 32. Therefore, thefirst gate electrode 26 is closer to the drain whereas the second gateelectrode 27 is closer to the source.

[0053] Here, the semiconductor chip thus provided with the dual gate FET7 is further provided with a resistor and/a capacitor, if necessary.Also provided is a transistor for constructing a current mirror circuit,as will be described hereinafter.

[0054] For such dual gate FET 7, a bias voltage is generated by theresistors R1, R2, R3, R5 and so on. This bias voltage hascharacteristics, as illustrated in FIG. 2.

[0055]FIG. 2 is a graph illustrating correlations between a controlvoltage (e.g., the external control voltage) Vapc and a gate voltage(e.g., the voltage at the first gate G₁ or the voltage at the secondsecond gate G₂). Letters Vg1 designate the voltage characteristics ofthe first gate G₁, and letters Vg2 designate the voltage characteristicsof the second gate G₂. Both of these characteristics exhibit alinearity, the gradients of which are steeper at the voltagecharacteristics Vg1 than at the voltage characteristics Vg2. In thegraph, a control voltage V₁ and a first gate G₁ voltage V₃ are set toequal levels such as about 2 to 2.5 V. When the control voltage Vapc isat the level V₁, moreover, a voltage V₂ to be applied to the second gateG₂ is set to about one half of the level V₃.

[0056] Therefore, the FET to act at the first gate closer to the drainof the dual gate FET acts (ON) faster than the FET to act at the secondgate closer to the source of the dual gate FET but does not act (OFF)later than the FET to act at the second gate closer to the source. As aresult, it is possible to reduce the noise in the OFF state. On theother hand, the change in a mutual conductance g_(m) of the FET to actat the first gate is larger than that of the FET to act at the secondgate. In other words, there is achieved an effect that the gain controlrange is widened.

[0057] The high frequency power amplifier module 1 of Embodiment 1 isconstructed such that the control voltage Vapc is fed to the first gateG₁ of the dual gate FET 7. When the system is OFF, therefore, no voltageis applied to the first gate G₁ so that the second gate G₂ and the draincan be electrically isolated to reduce the leakage (or noise)transmission of the input power from the second gate G₂ to the drain.This circuit construction can also be employed in the GSM system ofnon-linear actions (for the saturated actions) or the EDGE system oflinear actions to achieve the noise reduction in the system OFF state.

[0058] The high frequency power amplifier module 1 of Embodiment 1 hasan effect for improving the AM-AM conversion. FIG. 3 is a graph plottingthe AM-AM conversion characteristics. The abscissa indicates the powerPin (in dBm) of the input signal Pin, and the ordinate indicates anAMout (or the AM-AM conversion). In the case of the single gate, theoutput power at the measuring time is controlled to a constant value,but the voltage Vapc has a tendency to be lowered as the input powerincreases. As exemplified by the single gate MOSFET, therefore, theAM-AM conversion (AMout) grows the higher (or the worse) as the inputpower increases. The reduction in the voltage Vapc implies the reductionin the gate bias voltage of the single gate MOSFET. When the gate biasvoltage is lowered, the MOSFET does the amplification in the non-linearregion near the threshold voltage so that the output waveform isdistorted to have a worse AM distortion.

[0059] Even in case the dual gate MOSFET is employed as in Embodiment 1(of FIG. 1), on the contrary, the AMout is improved, as shown in FIG. 3.This is an example of the comparison between the case of the servicefrequency band of 880 MHz of the GSM and the case of 915 MHz. In thedual gate MOSFET, a relatively high bias voltage is applied to the gateof the drain side MOSFET so as to prevent the power voltage to beapplied to the source side MOSFET from drastically dropping. In short,there is applied a higher gate bias voltage than that of the single gateMOSFET. Therefore, the gate bias voltage is set to a higher level thanthe threshold voltage of the drain side MOSFET so that theamplifications are performed in a more linear region to reduce thedistortion of the output. As a result, the AM distortion is improved. Inother words, the single gate MOSFET operates in a state approximate theclass “C” amplifier. In the dual gate MOSFET, for an equal output power,the balance between the power voltage and the gate bias voltage can bechanged to a state approximate the class “A” amplifier, thereby toreduce the distortion of the waveform.

[0060] Here, the AM-AM conversion characteristics indicate thedistortion which is made at the output side when an amplitude-modulatedsignal is superposed on the carrier wave.

[0061] As the effects for the AM-AM conversion, on the other hand,similar improvements and effects can also be expected, in the case ofthe multistage amplifications of the circuit of FIG. 1: when used (1) atthe input stage (or the first stage) in the two-stage amplifier; (2) atthe input stage or the drive stage (or the second stage) of athree-stage amplifier; and (3) at the input stage and the drive stage ofthe three-stage amplifier.

[0062] Embodiment 1 has been described on the high frequency poweramplifier module which packages the single semiconductor amplificationelement, but the invention could also be applied to the high frequencypower amplifier module of the multistage amplifier construction in whichthe plurality of semiconductor amplification elements are sequentiallycascade-connected, as has been described hereinbefore.

[0063] As a more specific embodiment of the invention, here will bedescribed with reference to FIGS. 5 and 6 a high frequency poweramplifier module of a three-stage amplifier construction which canperform the amplifications of the GSM system and the EDGE system byswitching the modes. FIG. 5 is a circuit diagram of the high frequencypower amplifier module of Embodiment 1, and FIG. 6 is a block diagramshowing a construction of a wireless communication system (or a mobilephone) packaging the high frequency power amplifier module of Embodiment1.

[0064] The high frequency power amplifier module 1 of this embodiment isconstructed, as shown in FIG. 5, to have three stage amplifications, ofwhich the first stage (or the input stage) uses the transistor T1 havingthe dual gate FET structure whereas the second stage (or the drivestage) and the third stage (or the final stage: the output stage) use asingle gate Si-MOSFETs (i.e., transistors T2 and T3).

[0065] The transistors T1, T2 and T3 are sequentially cascade-connectedbetween the input terminal 2 and the output terminal 3, and matchingcircuits M1 to M4 are interposed between the individual stages. On theother hand, the drain terminals D of the individual transistors T1, T2and T3 are connected through microstrip lines MS2, MS4 and MS5 and coilsL2, L3 and L4 with the first voltage terminal 4 to be fed with the firstreference potential Vdd. Between the first voltage terminal 4 and theindividual coils L2, L3 and L4, on the other hand, there are connectedin parallel capacitors C5 to C7 which are connected at their one-endelectrodes with the ground. Here, the coils may be parasitic.

[0066] On the other hand, each stage is provided with a bias circuit, acurrent mirror circuit for temperature compensations, and a modeswitching circuit for switching the modes of the GSM system and the EDGEsystem. In order to construct the current mirror circuit: a currentmirror circuit transistor T_(CM) 1 of the dual gate FET construction ismonolithically formed in the semiconductor chip to be used at the firststage; a current mirror circuit transistor T_(CM) 2 of the single gateFET construction is monolithically formed in the semiconductor chip tobe used at the second stage; and a current mirror circuit transistorT_(CM) 3 of the single gate FET construction is monolithically formed inthe semiconductor chip to be used at the third stage.

[0067] The mode switching circuit is provided with mode switchingtransistors (MOSFETs) T_(SW) 1 to T_(SW) 3 which are connected at theirgate electrodes with a mode switching terminal 9 through resistors R4,R9 and R13, respectively.

[0068] The bias circuit is constructed to include individually threesets of resistors (R1 to R3, R6 to R8, and R10 to R12) which areconnected at their one-end terminals with nodes a, c and d,respectively. The first transistors R1, R6 and R10 are connected withthe control terminal 6; the second transistors R3, R8 and R12 areconnected with the gate electrodes G of the transistors T1, T2 and T3(e.g., the second gate G₂ of the transistor T1); and the third resistorsR2, R7 and R11 are connected with the drains of the mode switchingtransistors T_(SW) 1 to T_(SW) 3 and the gates G of the current mirrorcircuit transistors T_(CM) 1 to T_(CM) 3 (e.g., the second gate G₂ ofthe transistor T_(CM) 1)

[0069] The drains of the current mirror circuit transistors T_(CM) 1 toT_(CM) 3 are connected with the nodes a, c and d and further with thegates G of the transistors T_(CM) 1 to T_(CM) 3 (e.g., the second gateG₂ of the transistor T_(CM) 1) through the resistors R2, R7 and R11. Onthe other hand, the mode switching transistors T_(SW) 1 to T_(SW) 3 andthe current mirror circuit transistors T_(CM) 1 to T_(CM) 3 are groundedat their sources to the earth.

[0070] At the first stage, on the other hand, the control terminal 6 isconnected through the resistor R5 with the individual first gates G₁ ofthe transistor T1 and the current mirror circuit transistor T_(CM) 1.

[0071] The high frequency power amplifier module 1 thus is constructedis packaged in the cellular mobile phone (or the wireless communicationsystem), as shown in FIG. 6. In FIG. 6: the first stage, as constructedof the dual gate FET 7 or the like of the high frequency power amplifiermodule 1, is an amplifier A1; the second state is an amplifier A2; andthe third stage is an amplifier A3, of which the amplifier A1 ispartially shown in the same state as that of FIG. 1.

[0072] In the mobile phone, the input terminal 2 of the high frequencypower amplifier module 1 is connected with a radio signal generator 11.This radio signal generator 11 receives a voice or a data signal, andconverts it and outputs a high frequency signal. This output signal isfed as the input signal Pin to the input terminal 2.

[0073] The control signal (or the APC signal) is processed by a variablebias circuit 12, the output of which is fed as the control voltagesignal Vapc to the control terminal 6.

[0074] The mobile phone is operated, each time it is used, with itsselect keys to select either the GSM system or the EDGE system.Specifically, the mode switching signal, the state of whichis-determined by the operation of the select keys, is fed to a modeswitching circuit 13 to turn ON/OFF a switch 14. Thus, the modeswitching circuit 13 generates a mode switching signal voltage accordingto the operation of the select keys, so that the mode switching signalvoltage is fed to the mode switching terminal 9. The mode switchingtransistors T_(SW) 1 to T_(SW) 3 are controlled by that mode switchingsignal.

[0075] The high frequency power amplifier module 1 is connected at itsoutput terminal 3 with a transmission/reception change-over switch 15.With this transmission/reception change-over switch 15, there isconnected not only a receiving circuit 16 but also an antenna 17.

[0076] On the other hand, the output power, as outputted from the outputterminal 3, is detected by a detector 18. The detection result of thisdetector 18 is fed to a not-shown APC circuit, from which theaforementioned APC signal is outputted.

[0077] Here will be described the GSM mode and the EDGE mode withreference to FIGS. 6 and 5.

[0078] In the GSM mode, the mode switching circuit 13 is turned ON sothat a voltage exceeding a constant level is applied to the modeswitching terminal 9. When the voltage exceeding the constant level isapplied to the mode switching terminal 9, the mode switching transistorT_(SW) 1 is biased at its gate so that it is turned ON. When the modeswitching transistor T_(SW) 1 is turned ON, the resistance of (R1+R2)overcomes the ON resistance of the mode switching transistor T_(SW) 1sufficiently so that the potential of a node e becomes substantiallyequal to the ground potential. Therefore, the current mirror circuittransistor T_(CM) 1 is in the off state. As a result, a current I₂ doesnot flow between the drain and source of the current mirror circuittransistor T_(CM) 1. At this time, a bias current I₁ is caused to flowby the voltage applied from the variable bias circuit 12 so that thevoltage at the node a, as divided by the resistor R1 and the resistorR2, is applied to the second gate G₂ of the dual gate FET 7 composingthe first stage transistor T1.

[0079] In the GSM mode, the output powers of the second and third stageamplifiers A2 and A3 are also controlled as at the first stage by thevoltage which is generated by the variable bias circuit 12. In the GSMmode, the power amplifier module is employed in the non-linear action sothat the maximum output power is about 35 dBm.

[0080] In the EDGE mode, the mode switching circuit 13 is turned OFF sothat a voltage at a constant (about 0 V) or lower level is applied tothe mode switching terminal 9. As a result, the mode switchingtransistor T_(SW) 1 is biased at its gate with substantially 0 V so thatit is turned OFF. In the EDGE mode, on the other hand, the bias voltage,as generated by the variable bias circuit 12, is fixed at an arbitraryvalue (for which a plurality of values may be prepared and changed forthe situations). In this case, the output power Pout is controlled bychanging the magnitude of an input signal RFin (or Pin). Upstream of theinput terminal 2, more specifically, there is provided a gain controlcircuit, by which the magnitude of the input signal Pin is changed tochange the magnitude of the output power Pout.

[0081] When the mode switching transistor T_(SW) 1 is turned OFF, nocurrent flows between the node a (at the potential of the second gate G₂of the current mirror circuit transistor T_(CM) 1) and the node e (atthe potential of the drain of the mode switching transistor T_(SW) 1) sothat the node a and the node e take the same potential.

[0082] In the state where an arbitrary voltage for the EDGE actions isapplied from the variable bias circuit 12, a predetermined bias isapplied to both the first gate G₁ and the second gate G₂ of the currentmirror circuit transistor T_(CM) 1. As a result, the current mirrorcircuit transistor T_(CM) 1 is ON. At this time, the bias current I₂ iscaused to flow by the voltage applied from the variable bias circuit 12.Since the second gate G₂ and the drain of the current mirror circuittransistor T_(CM) 1 are at the same potential, the current mirrorcircuit transistor T_(CM) 1 acts to set the current I₂ to a constantlevel so long as the voltage from the variable bias circuit 12 does notchange. In this embodiment, on the other hand, the dual gate FET 7 andthe current mirror circuit transistor T_(CM) 1 are fabricated with thesame structure in the common semiconductor chip but have different gatewidths (that is, the current mirror circuit transistor T_(CM) 1 is givena size as large as one N-th of the dual gate FET 7 (i.e., the transistorT1), where N is a real number). The current mirror circuit transistorT_(CM) 1 and the dual gate FET 7 construct the current mirror circuit toperform the current mirror action. In this case, the node e, the node aand the second gate G₂ Of the transistor T1 (or the dual gate FET 7) areat the same potential. As a result, the current mirror is establishedbetween the current I₂ to flow through the control voltage signal: Vapc,the resistor R1 and the current mirror circuit transistor T_(CM) 1, andthe electric current to flow through the power voltage Vdd, the coil L2,the microstrip line MS2 and the dual gate transistor T1. The current I₂is determined by the characteristics of the control voltage signal Vapc,the resistor R1 and the transistor T_(CM) 1. In case the gate has thewidth N, an idle current as high as N times of the current I₂ flowsbetween the drain and source of the dual gate FET 7 (i.e., thetransistor. T1).

[0083] In the EDGE mode, the linear action is made to provide themaximum output power of about 29 dBm. Since the EDGE mode is linear, itis not desired to change the output power by changing the bias voltage.Therefore, the control voltage signal Vapc takes a constant value sothat the amplitude of the input signal Pin to be fed to the inputterminal 2 is controlled to set the output power to a desired value.This control is performed by an AGC using an attenuator to be connectedwith the input terminal 2.

[0084] In addition to the effects of Embodiment 1, according to thisembodiment, the gradient (or slope) of the increase in the output powerper unit bias voltage applied to the control terminal 6 becomes gentleto improve the controllability of the power control. Therefore, it ispossible to control the output power to a low power level. Moreover, theoutput power is easily controlled from the outside.

[0085] (Embodiment 2)

[0086]FIG. 7 is a graph plotting isolation characteristics betweeninput/output terminals in the high frequency power amplifier moduleaccording to another embodiment (or Embodiment 2) of the invention.

[0087] In Embodiment 2, although not especially presented in a circuitdiagram, the high frequency power amplifier module has a two-stageamplifying construction of a first stage (or an input stage) and asecond stage, of which the first stage is constructed to include thedual gate FET 7 as in Embodiment 1 whereas the second stage isconstructed to include a single gate Si-MOSFET. In other words, thefirst stage acts as a drive stage for the single gate Si-MOSFET or theoutput stage.

[0088] As compared with the three-stage amplifier, the two-stageamplifier is lowered in the isolation characteristics in which the inputpower leaks from the output terminal, but this isolation can beimproved, as shown in FIG. 7, by using the dual gate FET as the driverstage of the two-stage amplifier.

[0089] Generally, the two-stage construction of the amplifier is lowerin the gain than the three-stage construction so that a higher inputpower is needed for the same output power. Especially in the GSM mode,the output power of the output stage transistor is controlled for aconstant input power with the voltage which is generated by the variablebias circuit. By using the single gate MOSFET as in the prior art, theaforementioned input power is increased to raise the gate potential ofthe input stage transistor of the amplifier. As a result, an inputsignal at a certain value or higher enters even if the gate bias of theinput stage transistor is set to 0 V. When this input signal exceeds athreshold voltage V_(th) of the input stage transistor, this input stagetransistor is turned ON by forming its channel. When the high frequencypower amplifier module is adopted in the mobile phone, the power switchor the like is not employed for lowering the power voltage and forreducing the current consumption, but the high frequency power amplifiermodule is often connected directly with the power source so that itreceives the power voltage at all times. As a result, the input signalwill leak to the output side.

[0090] When the dual gate FET is employed, on the other hand, no channelis formed for the first gate G₁ of the dual gate FET to apply no voltageto the drain on the side of the second gate G₂, if the voltage of thevariable bias circuit is lowered over the threshold voltage V_(th). Evenwhen a high input signal is inputted to the second gate G₂ to exceed thethreshold voltage V_(th), therefore, no channel is formed for the secondgate G₂. As a result, it is possible to suppress the leakage power.Therefore, the leakage power after the improvement can be made as smallas the leakage due to the coupling by the parasitic capacity or thelike.

[0091] The circuit can be simplified because the input/output terminalscan be easily isolated. Therefore, it is possible to reduce the size ofthe high frequency power amplifier module 1 and accordingly the size ofthe wireless communication system.

[0092] Here, the AM-AM conversion can also be improved by using the dualgate FET in the driver stage of the two-stage amplifier construction.

[0093] (Embodiment 3)

[0094]FIG. 8 is a circuit diagram of a high frequency power amplifiermodule according to another embodiment (or Embodiment 3) of theinvention, and FIG. 9 is a graph illustrating correlations between anexternal control voltage in a high frequency power amplifier module anda gate voltage of the MOSFET 7.

[0095] In the circuit of Embodiment 1, according to Embodiment 3, adiode D1 is connected in series between the node b connected with thecontrol terminal 6 and the resistor R5, and a resistor R14, as connectedat its one electrode with the ground, is connected at its otherelectrode between the first gate G₁ of the dual gate FET 7 and theresistor R5. By packaging that diode D1, as shown in FIG. 9, the rise ofthe potential in the first gate G₁ of the dual gate FET 7 shifts from 0to a plus voltage (or an offset voltage). As a result, the isolationeffect when the voltage Vapc is set to 0 V can set the potential Vg1 ofthe gate G₁ to the ground potential even if a residual voltage (e.g.,about 0.2 to 0.5 V) is in the voltage Vapc so that the effect can bemore reliably attained than the cases of Embodiment 1 and Embodiment 2.

[0096] Here, the circuit can be employed in both the single-stageamplifier construction and the multistage amplifier construction.

[0097] (Embodiment 4)

[0098]FIG. 10 is a circuit diagram of a high frequency power amplifiermodule according to another embodiment (or Embodiment 4) of theinvention, and FIG. 11 is a graph illustrating correlations between anexternal control voltage in a high frequency power amplifier module anda gate voltage of the MOSFET 7.

[0099] In Embodiment 4, the control voltage is generated by a voltagedivider which is connected between the first gate G₁ of the first stagedual gate FET 7 and the control terminal 6 and which is constructed toinclude resistors R15 to R17. This control voltage is the output, i.e.,a control voltage Vagc of the not-shown AGC (Auto Gain Control) circuit.

[0100] The gate G₂ of the first stage dual gate FET 7 is fed as inEmbodiment 1 with the input signal Pin from the input terminal 2 and acontrol voltage Vg from the gate control terminal 10. A bias voltage isapplied to the gates of the transistors T1, T2 and T3 (e.g., to thesecond gate G₂ in the transistor T1) by a bias circuit which has first,second and third stages constructed to include three resistors (R18 toR20, R21 to R23, and R24 to R26), respectively.

[0101] In Embodiment 4, the correlations between the external controlvoltage and the gate voltage are illustrated in FIG. 11. In Embodiment4, the second gate G₂ is set to a constant potential. As a result, theoutput power and the gain can be controlled with the change in theapplied voltage to the gate G₁, and the fluctuation of the inputimpedance of the gate G₂ at the output power control time can besuppressed. Thus, there is obtained an effect for suppressing theaffections on the radio signal generator on the input side.

[0102] According to Embodiment 4, on the other hand, it is possible toincorporate the function (i.e., the control function by the AGC circuit)which has to be added in the prior art from the outside.

[0103] Although our invention has been specifically described on thebasis of its embodiments, it should not be limited to the embodimentsbut could naturally be modified in various manners without departingfrom the gist thereof. For example, the semiconductor amplificationelement can be likewise applied with similar effects even if it is madeof a compound semiconductor of GaAs or the like. On the other hand, thedual gate FET could also be constructed by preparing two transistorscorresponding to the gate G₁ and the gate G₂ and by connecting the twotransistors in a manner to have a series connection in theirdrain-source paths.

[0104] The effects to be obtained from the representative of theinventions, as disclosed herein, will be briefly described in thefollowing.

[0105] It is possible to provide a high frequency power amplifiermodule, in which the GSM system (for the saturated actions) and the EDGEsystem (for the linear actions) are compatible in the common circuit,and a wireless communication system.

[0106] It is possible to provide a high frequency power amplifier modulecapable of improving the AM-AM conversion, and a wireless communicationsystem.

[0107] It is possible to provide a high frequency power amplifier modulewhich finds it easy to isolate the input/output terminals and it hard tocause the signal leakage, and a wireless communication system.

[0108] Because the input/output terminals can be easily isolated, thecircuit can be simplified to provide a small-sized high frequency poweramplifier module and a small-sized wireless communication system.

[0109] It is possible to provide a high frequency power amplifier modulewhich can be easily power-controlled.

What is claimed is:
 1. A high frequency power amplifier modulecomprising: an input terminal adapted to be fed with a signal to beamplified; an output terminal; a control terminal; and a semiconductoramplification element including: a source; a drain for outputting asignal to said output terminal; and a first gate and a second gatebetween said drain and said source, said first gate being closer to saiddrain for receiving the signal from said control terminal, and saidsecond gate being closer to said source for receiving the signal fromsaid input terminal.
 2. A high frequency power amplifier moduleaccording to claim 1, wherein said semiconductor amplification elementis a dual gate type semiconductor amplification element.
 3. A highfrequency power amplifier module according to claim 1, wherein said highfrequency power amplifier module is a high frequency power amplifiermodule for the GSM.
 4. A high frequency power amplifier module accordingto claim 1, wherein said high frequency power amplifier module is a highfrequency power amplifier module for the EDGE.
 5. A high frequency poweramplifier module comprising: an input terminal; an output terminal; acontrol terminal; a semiconductor amplification element including afirst gate and a second gate between a drain and a source, said firstgate being closer to said drain for receiving the signal from saidcontrol terminal, and said second gate being closer to said source forreceiving the signal from said input terminal; a circuit for feeing saidoutput terminal with a signal according to the signal outputted fromsaid semiconductor amplification element; and a bias circuit connectedwith said control terminal for feeding the second gate of saidsemiconductor amplification element with a bias according to a controlvoltage fed to said control terminal.
 6. A high frequency poweramplifier module according to claim 5, wherein said bias has non-linearcharacteristics.
 7. A high frequency power amplifier module according toclaim 6, wherein said high frequency power amplifier module is a highfrequency power amplifier module for the GSM.
 8. A high frequency poweramplifier module according to claim 7, wherein both an FET acting at thefirst gate and an FET acting at the second gate of said dual gate FETexhibit linear voltage characteristics, and wherein the voltagecharacteristics of the FET acting at said first gate have a steepergradient than that of the voltage characteristics of the FET acting atsaid second gate.
 9. A high frequency power amplifier module accordingto claim 7, wherein the bias voltage is so applied to said dual gate FETthat an FET acting at the first gate of said dual gate FET acts quickerthan an FET acting at said second gate and stops its actions slower thanthe FET acting at said second gate.
 10. A high frequency power amplifiermodule comprising: an input terminal; an output terminal; a controlterminal; a mode switching terminal; a semiconductor amplificationelement including a first gate and a second gate between a drain and asource, said first gate being closer to said drain for receiving thesignal from said control terminal, and said second gate being closer tosaid source for receiving the signal from said input terminal; a circuitfor feeing said output terminal with a signal according to the signaloutputted from the drain of said semiconductor amplification element; abias circuit connected with said control terminal for feeding the secondgate of said semiconductor amplification element with a bias accordingto a control voltage fed to said control terminal; and a mode switchingcircuit activated in response to the signal from said mode switchingterminal to feed an output signal to the second gate of saidsemiconductor amplification element.
 11. A high frequency poweramplifier module according to claim 10, wherein said circuit disposedbetween said semiconductor amplification element and said output circuitincludes one or more cascade-connected second semiconductoramplification elements, and wherein said second semiconductoramplification element includes: a control terminal connected with theoutput terminal of the upstream stage semiconductor amplificationelement; and a first terminal connected with either said output terminalor the downstream stage semiconductor amplification element.
 12. A highfrequency power amplifier module according to claim 11, furthercomprising: an AGC circuit for feeding its output to the first gate ofsaid semiconductor amplification element.
 13. A high frequency poweramplifier module according to claim 10, wherein said high frequencypower amplifier module is an amplifier system for the GSM, when theoutput signal of said mode switching circuit exhibits a first state, andan amplifier system for the EDGE when the output signal of said modeswitching circuit exhibits a second state.
 14. A high frequency poweramplifier module comprising: an input terminal; an output terminal; acontrol terminal; a mode switching terminal; a semiconductoramplification element including a first gate and a second gate between adrain and a source, said first gate being closer to said drain forreceiving the signal from said control terminal, and said second gatebeing closer to said source for receiving the signal from said inputterminal; a circuit for feeing said output terminal with a signalaccording to the signal outputted from the drain of said semiconductoramplification element; a bias circuit connected with said controlterminal for feeding the first gate and the second gate of saidsemiconductor amplification element with a bias according to a controlvoltage fed to said control terminal; and a mode switching circuitactivated in response to the signal from said mode switching terminal tofeed an output signal to the second gate of said semiconductoramplification element.
 15. A high frequency power amplifier moduleaccording to claim 14, wherein said high frequency power amplifiermodule is an amplifier system for the GSM, when the output signal ofsaid mode switching circuit exhibits a first state, and an amplifiersystem for the EDGE when the output signal of said mode switchingcircuit exhibits a second state.
 16. A wireless communication systemcomprising a high frequency power amplifier module at the output stageon a transmission side, wherein said high frequency power amplifiermodule includes: an input terminal adapted to be fed with a signal to beamplified; an output terminal; a control terminal; and a semiconductoramplification element including: a source; a drain for outputting asignal to said output terminal; and a first gate and a second gatebetween said drain and said source, said first gate being closer to saiddrain for receiving the signal from said control terminal, and saidsecond gate being closer to said source for receiving the signal fromsaid input terminal.
 17. A wireless communication system according toclaim 16, wherein said semiconductor amplification element is a dualgate type semiconductor amplification element.
 18. A wirelesscommunication system according to claim 16, wherein said high frequencypower amplifier module is a high frequency power amplifier module forthe GSM.
 19. A wireless communication system according to claim 16,wherein said high frequency power amplifier module is a high frequencypower amplifier module for the EDGE.
 20. A wireless communication systemcomprising a high frequency power amplifier module at the output stageon a transmission side, wherein said high frequency power amplifiermodule includes: an input terminal; an output terminal; a controlterminal; a semiconductor amplification element including a first gateand a second gate between a drain and a source, said first gate beingcloser to said drain for receiving the signal from said controlterminal, and said second gate being closer to said source for receivingthe signal from said input terminal; a circuit for feeing said outputterminal with a signal according to the signal outputted from saidsemiconductor amplification element; and a bias circuit connected withsaid control terminal for feeding the second gate of said semiconductoramplification element with a bias according to a control voltage fed tosaid control terminal.
 21. A wireless communication system according toclaim 20, wherein said bias has non-linear characteristics.
 22. Awireless communication system according to claim 20, wherein said highfrequency power amplifier module is a high frequency power amplifiermodule for the GSM.
 23. A wireless communication system according toclaim 22, wherein both an FET acting at the first gate and an FET actingat the second gate of said dual gate FET exhibit linear voltagecharacteristics, and wherein the voltage characteristics of the FETacting at said first gate have a steeper gradient than that of thevoltage characteristics of the FET acting at said second gate.
 24. Awireless communication system according to claim 22, wherein the biasvoltage is so applied to said dual gate FET that an FET acting at thefirst gate of said dual gate FET acts quicker than an FET acting at saidsecond gate and stops its actions slower than the FET acting at saidsecond gate.
 25. A wireless communication system comprising a highfrequency power amplifier module at the output stage on a transmissionside, wherein said high frequency power amplifier module includes: aninput terminal; an output terminal; a control terminal; a mode switchingterminal; a semiconductor amplification element including a first gateand a second gate between a drain and a source, said first gate beingcloser to said drain for receiving the signal from said controlterminal, and said second gate being closer to said source for receivingthe signal from said input terminal; a circuit for feeing said outputterminal with a signal according to the signal outputted from the drainof said semiconductor amplification element; a bias circuit connectedwith said control terminal for feeding the second gate of saidsemiconductor amplification element with a bias according to a controlvoltage fed to said control terminal; and a mode switching circuitactivated in response to the signal from said mode switching terminal tofeed an output signal to the second gate of said semiconductoramplification element.
 26. A wireless communication system according toclaim 25, wherein said circuit disposed between said semiconductoramplification element and said output circuit includes one or morecascade-connected second semiconductor amplification elements, andwherein said second semiconductor amplification element includes: acontrol terminal connected with the output terminal of the upstreamstage semiconductor amplification element; and a first terminalconnected with either said output terminal or the downstream stagesemiconductor amplification element.
 27. A wireless communication systemaccording to claim 26, further comprising: an AGC circuit for feedingits output to the first gate of said semiconductor amplificationelement.
 28. A wireless communication system according to claim 25,wherein said high frequency power amplifier module acts as anamplification module for the GSM, when the output signal of said modeswitching circuit exhibits a first state, and an amplification modulefor the EDGE when the output signal of said mode switching circuitexhibits a second state.
 29. A wireless communication system comprisinga high frequency power amplifier module at the output stage on atransmission side, wherein said high frequency power amplifier moduleincludes: an input terminal; an output terminal; a control terminal; amode switching terminal; a semiconductor amplification element includinga first gate and a second gate between a drain and a source, said firstgate being closer to said drain for receiving the signal from saidcontrol terminal, and said second gate being closer to said source forreceiving the signal from said input terminal; a circuit for feeing saidoutput terminal with a signal according to the signal outputted from thedrain of said semiconductor amplification element; a bias circuitconnected with said control terminal for feeding the first gate and thesecond gate of said semiconductor amplification element with a biasaccording to a control voltage fed to said control terminal; and a modeswitching circuit activated in response to the signal from said modeswitching terminal to feed an output signal to the second gate of saidsemiconductor amplification element.
 30. A wireless communication systemaccording to claim 29, wherein said high frequency power amplifiermodule acts as an amplification module for the GSM, when the outputsignal of said mode switching circuit exhibits a first state, and anamplification module for the EDGE when the output signal of said modeswitching circuit exhibits a second state.
 31. A high frequency poweramplifier module comprising: an input terminal adapted to be fed with asignal to be amplified; an output terminal; a control terminal; a modeswitching terminal; a semiconductor element including: a source; a drainfor outputting a signal to be transmitted to said output terminal; afirst gate being disposed closer to said drain; and a second gatedisposed closer to said source and adapted to be fed with the signalfrom said input terminal; and a control circuit for receiving a signalfrom said control terminal and a signal from said mode switchingterminal to feed a bias voltage to said first gate and said second gate.32. A high frequency power amplifier module according to claim 31,wherein in response to the signal from said mode switching terminal,said control circuit generates the bias voltage so that saidsemiconductor element may act in a linear action region or in anon-linear action region.
 33. A high frequency power amplifier moduleaccording to claim 32, wherein said semiconductor element is a dual gateFET.
 34. A wireless communication system comprising: an antenna; and ahigh frequency power amplifier module for feeding its output to saidantenna, wherein said high frequency power amplifier module includes: aninput terminal adapted to be fed with a signal to be amplified; anoutput terminal; a control terminal; a mode switching terminal; asemiconductor element including: a source; a drain for outputting asignal to be transmitted to said output terminal; a first gate beingdisposed closer to said drain; and a second gate disposed closer to saidsource and adapted to be fed with the signal from said input terminal;and a control circuit for receiving a signal from said control terminaland a signal from said mode switching terminal to feed a bias voltage tosaid first gate and said second gate.
 35. A wireless communicationsystem according to claim 34, wherein in response to the signal fromsaid mode switching terminal, said control circuit generates the biasvoltage so that said semiconductor element may act in a linear actionregion or in a non-linear action region.
 36. A wireless communicationsystem according to claim 35, wherein said semiconductor element is adual gate FET.